(1) Field of the Invention
The present invention generally relates to a logic circuit, and more particularly to a logic circuit using, for example, a C-MOS static circuit.
(2) Description of the Related Art
In recent years, due to a request for a high speed operation in a semiconductor integrated circuit, it is required that each of circuits arranged in the semiconductor integrated circuit can be operated at a high speed.
FIG. 1 shows a structure of an MPU system. Referring to FIG. 1, an MPU 31 is coupled to a main memory 32. The MPU 31 has a data processing portion 33, a high speed address conversion buffer (a TLB portion) 34 and a TAG portion 35 for adding identification information to data. The MPU 31 carries out a data processing for data read out from the main memory 32. The MPU 31 has a function by which if data which has been read out from the main memory 32 is stored in the MPU 31, the data is not read out therefrom again. This function will be described below with reference to FIG. 2.
Referring to FIG. 2, the TAG portion 35 has a memory 36 (formed, for example, of an S-RAM) and a comparing portion 37. Addresses of data stored in the inside of the MPU 31 are stored in the memory 36. The comparing portion 37 compares an address B corresponding to data requested by the TLB portion 34 to an address A stored in the memory 36. If the addresses A and B are identical to each other, the comparing portion 37 outputs a hit signal C.
The comparing portion 37 is formed of a logic circuit by which each bit of the address A from the memory 36 and a corresponding each bit of the address B from the TLB portion 34 are compared with each other. If all bits of the address A are identical to corresponding all bits of the address B, the hit signal C having a high level or a low level is supplied from the comparing portion 37 to the data processing portion 33. As a result, the data processing portion 33 is informed that it is not necessary to access the main memory 32.
FIG. 3A shows a structure of an example of a conventional logic circuit. This logic circuit is a NAND gate as symbolized in FIG. 3B.
Referring to FIG. 3A, the NAND gate is formed of N-channel MOS FET Q.sub.51 -Q.sub.54. Input terminals T.sub.IN41 and T.sub.IN42 are provided with a signal, and Input terminals T.sub.IN43 and T.sub.IN44 are provided with a signal B. A NAND logic operation of the signals A and B is carried out, so that an logical output signal C is output from an output terminal T.sub.OUT11.
The above signals A and B to be input the NAND gate must have a CMOS logic level. Thus, the memory 36 shown in FIG. 2 is provided with a sense amplifier 38 so that the signals amplified by the sense amplifier 38 are supplied to the comparing portion 37.
In the conventional logic circuit, signals must have a predetermined amplitude (e.g. the CMOS logic level) in the logical operation, and the logical operation of infinitesimal signals, such as signals output from a memory, can not be carried out. Thus, the infinitesimal signals are amplified by the sense amplifier so as to have the predetermined level at which the logical operation can be carried out. In this case, signals are supplied to the logic circuit through an amplifier, so that supply of the signals to the logic circuit is delayed by a time for which the signals reach the predetermined level. As a result, the logical operation of infinitesimal signals can not be carried out at a high rate.